Single electron devices, and particularly single electron memory cells, are presently of great interest, due to potential advantages in memory cell size and power dissipation, compared to memory technologies currently in use. As used herein, the term "single electron device" refers to an electronic device capable of providing a repeatable and measurable response to the presence or absence of a single electron.
As device sizes have shrunk over the last several decades, the number of electrons contributing to the drain current in field effect transistors ("FETs") used in memory devices has correspondingly decreased. Extrapolation from these trends suggests that in another decade, FETs will have drain currents including as few as ten electrons at a time. When so few electrons contribute to a current and therefore to a signal, normal fluctuations in the number of electrons present in a volume of semiconductor material can lead to uncertainty or error in the signal that the current represents.
Memories using single electron memory cells provide certainty in numbers of electrons representing data in a memory cell and therefore help to avoid problems due to fluctuations in the number of electrons that are present in a transistor at one time. Memory cells employing single electron transistors are also extremely simple and can be quite small. For example, a memory structure employing vertically stacked cells to provide an area per bit of 0.145 micrometers squared is described in "A 3-D Single-Electron-Memory Cell Structure with 2F.sup.2 per bit" by T. Ishii et al. (IEDM 97), pp. 924-926.
The combination of size, power requirements and simplicity make single electron structures promising candidates for very high capacity memory integrated circuits. This is discussed in more detail in "Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage" by K. Yano et al., 1996 Intl. Solid State Circuits Conf. (Feb. 9, 1996), pp. 266-267 and "A 128 Mb Early Prototype for Gigascale Single-Electron Memories" by K. Yano et al., 1998 Intl. Solid State Circuits Conf. (Feb. 7, 1998), pp. 344-345.
FIG. 1A is a simplified schematic diagram of a typical two-terminal single electron device 20, in accordance with the prior art. The single electron device 20 includes first 22 and second 24 electrodes and an island 26 formed from conductive material, which may be semiconductor material, as discussed in U.S. Pat. No. 5,731,598, entitled "Sincle Electron Tunnel Device And Method For Fabricating The Same" issued to H. Kado et al. (Mar. 24, 1998). The first 22 and second 24 electrodes are each separated from the island 26 by small insulating gaps 28, 28'. The first 22 and second 24 electrodes, the island 26 and the gaps 28, 28' are all collectively mounted on an insulating substrate 30 or are surrounded by an insulator. The gaps 28, 28' may be formed of any insulating material but must be small enough to allow conduction band electrons 32 (hereinafter "electrons") to tunnel through them in response to a voltage V coupled across the first 22 and second 24 electrodes. The voltage V is provided by an external source. represented in FIG. 1A by a battery 34.
A first condition for trapping one or more electrons 32 on the island 26 is that the resistance R between the island 26 and other structures on the substrate 30 must be greater than a quantum resistance R.sub.k, as is discussed, for example, in "Single-electron devices" by H. Ahmed et al. Microelectronic Engineering 32 (1996), pp. 297-315, and "Single electron electronics: Challenge for nanofabrication" by H. Ahmed, J. Vac. Sci. Technol. B 15(6) (Nov./Dec. 1997), pp. 2101-2108. When the first 22 and second 24 electrodes and the island 26 are mounted on the insulating substrate 30 and are surrounded by an insulator such as air. the primary resistance R between the island 26 and any other structure is set by tunneling resistances R.sub.t associated with the gaps 28, 28' separating the island 26 from the first 22 and second 24 electrodes. The quantum resistance R.sub.k equals h/q.sup.2, or about 26 k.OMEGA., where h is Planck's constant and q represents the charge of a single electron. This first condition will be satisfied for all of the examples considered herein but is included for completeness sake.
A second condition is that allowed states for these electrons 32 must be separated from a conduction band edge E.sub.C by an "electron charging energy" that is given as q.sup.2 /2C, where C represents a capacitance of the island 26. In other words, a first electron 32 that is introduced onto the island 26 will occupy an allowed state having a potential energy that is greater than that of the conduction band edge E.sub.C for the material forming the island 26 by q.sup.2 /2C.
A third condition is that, for the electron or electrons 32 to be trapped on the island 26, the electron charging energy q.sup.2 /2C must be substantially greater than an average thermal energy kT, or q.sup.2 /2C&gt;kT, where k represents Boltzmann's constant and T represents temperature in Kelvin. The capacitance C must be on the order of one attoFarad for electrons 32 to be trapped on the island 26 for any appreciable length of time at room temperature (kT=0.026 eV at room temperature). For example, an island 26 having a capacitance of 10.sup.-16 F is about 100 nanometers in diameter but can only exhibit single-electron effects at temperatures at or below about 4 Kelvin. Islands 26 having diameters of one to five nanometers exhibit significant single-electron effects at room temperature (circa 300 K).
FIG. 1B is a simplified potential energy diagram for the device 20 of FIG. 1A showing a potential well 40, in accordance with the prior art. FIG. 1B shows Fermi levels ("E.sub.F ") 42, 44 in the first 22 and second 24 electrodes, respectively, a lowest allowed state 46 for one electron 32 in the potential well 40 on the island 26, and eneray barriers 48, 48' associated with insulating materials forming the gaps 28, 28', respectively. An important property of the device 20 of FIG. 1A is that no significant current can flow through the device 20 until a magnitude of the potential V due to the external source 34 equals or exceeds the electron charging energy or V.gtoreq.q.sup.2 /2C. FIG. 1C is a simplified potential energy diagram illustrating the potential V setting the Fermi level 42 at the left side of the Figure equal to the lowest allowed state of the potential well 40, i.e., at the onset of conduction, in accordance with the prior art.
FIG. 1D is a simplified graph of an I-V characteristic 50 for the device 20 of FIG. 1A, in accordance with the prior art. The I-V characteristic 50 shows essentially no conduction until the applied voltage V reaches a threshold V.sub.C, causing the Fermi level 42 on the electron supply side to be equal to the electron charging energy q.sup.2 /2C. The region of essentially no conduction is known as the Coulomb blockade region. When the applied voltage V reaches the threshold V.sub.C, known as the Coulomb gap voltage. the energy barrier effectively vanishes. Linear I-V dependence is seen in FIG. 1D for voltages having an absolute magnitude exceeding V.sub.C.
FIG. 2 is a simplified schematic illustration of a typical field effect transistor ("FET") 60 that includes the island 26 of FIG. 1A for storing one or more electrons 32, in accordance with the prior art. The FET 60 includes all of the elements of the two-terminal device 20 of FIG. 1 and additionally includes a gate 62 having a capacitance C.sub.G and a gate bias supply 64. The gate bias supply 64 includes a first electrode coupled to the gate 62 and a second electrode coupled to one side of the supply 34 providing the voltage V. The FET 60 has a channel 66 formed from semiconductor material that is coupled to the first 22 and second 24 electrodes.
Several examples of FETs 60 capable of providing repeatable output signals indicative of single electron 32 storage on the islands 26 are described in "A Room-Temperature Silicon Single-Electron Metal-Oxide-Semiconductor Memory With Nanoscale Floating-Gate and Ultranarrow Channel" by L. Guo et al., Appl. Phys. Lett. 70(7) (Feb. 17, 1997), pp. 850-852 and "Fabrication And Characterization of Room Temperature Silicon Single Electron Memory" by L. Guo et al., J. Vac. Sci. Technol. B 15(6) (November/December 1997), pp. 2840-2843. Similar FETs 60 are described in "Room Temperature Operation of Si Single-Electron-Memory with Self-Aligned Floating Dot Gate" (IEDM 1996), pp. 952-954; Appl. Phys. Lett. 70(13) (Mar. 31, 1997), pp. 1742-1744 and "Si Single Electron Tunneling Transistor With Nanoscale Floating Dot Stacked on a Coulomb Island by Self-Aligned Process", Appl. Phys. Lett. 71(3) (Jul. 21, 1997), pp. 353-355, all by A. Nakajima et al. These FETs 60 employ feature sizes as small as 30 nanometers and require much closer alignment between elements than 30 nanometers. Formation of such small feature sizes using electron beam lithography does not presently lend itself to mass production.
These FETs 60 employ a floating island 26 between the gate 62 and the channel 66 to modulate conductivity in the channel 66. In these FETs 60, the island 26 spans the width of the channel 66.
It will be appreciated that other techniques for forming the islands 26 may be emploved. For example, shallow implantation of relatively high doses (e.g., ca. 5-50.times.10.sup.14 /cm.sup.2) of silicon or germanium at relatively low energies (e.g., ca. 20 keV) into relatively thin (e.g., ca. 5-20 or more nanometers) silicon dioxide layers, followed by annealing, provides islands 26 formed from nanocrystals of the implanted species that are insulated from each other and from an underlying silicon region, as described in "Fast and Long Retention-Time Nano-Crystal Memory" by H. Hanafi et al., IEEE Trans. El. Dev., Vol. 43, No. 9 (Sep. 1996), pp. 1553-1558. Performance of memories using islands 26 formed from nanocrvstals in proximity to the channel 66 is discussed in "Single Charge and Confinement Effects in Nano-Crystal Memories" by S. Tiwari et al., Appl. Phys. Lett. 69(9) (Aug. 26, 1996), pp. 1232-1234.
Prior art FETs may provide multiple islands 26 between the gate 62 and the channel 66. and are capable of storing multiple electrons 32. As a result these FETs are analogous to conventional flash memories and are capable of multilevel signal storage and readout. An example of an arrangement for discriminating between multiple signal levels that may represent a stored signal is given in "Novel Level-Identifying Circuit for Multilevel Memories" by D. Montanari et al., IEEE Jour. Sol. St. Cir., Vol. 33, No. 7 (July 1998), pp. 1090-1095.
FETs 60 including one or more islands 26 suitable for capture of electrons 32 thus are able to provide measurable and repeatable changes in their electrical properties in response to capture of the electron or electrons 32 on at least one island 26. Moreover, these FETs 60 provide these changes in a convergent manner, i.e., the changes may be produced by storage of a single electron 32, and storage of that single electron 32 can inhibit storage of another electron 32. In this way, some of the FETs 60 avoid some problems due to number fluctuations in the population of electrons 32 that could otherwise be troublesome for FETs 60 having very small populations of electrons 32.
Additionally, the energy barriers 48, 48' cause the single electron device 20 and the FETs 60 to store trapped electrons 32 for significant periods of time, even in the absence of externally applied electrical power (e.g., voltage sources 34, 64). As a result, a nonvolatile memory function is provided by these devices 20 and FETs 60.
While single electron devices 20 and FETs 60 show great promise as memory cells for very high density memory arrays, fabrication difficulties prevent mass production of memory arrays using these devices 20, 60 as memory cells. Difficulties in regulating the size of the island or islands 26 and the thickness of the surrounding dielectric materials forming the gaps 28, 28' cause problems, particularly with respect to uniformity of device characteristics across many similar devices on a wafer or substrate. Difficulties in realizing the fine line interconnections (e.g., ca. 0.4 micron pitch) and other needed elements also cause poor yields in fabrication of these devices 20, 60.
There is therefore a need for a method for fabricating single electron devices that is robust and that provides reproducible single-electron device characteristics.